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1 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom december 2001 ?2001 fairchild semiconductor corporation fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom general description fm24c128 is a 128kbit cmos non-volatile serial eeprom organized as 16k x 8 bit memory. this device confirms to extended iic 2-wire protocol that allows accessing of memory in excess of 16kbit on an iic bus. this serial communication protocol uses a clock signal (scl) and a data signal (sda) to synchro- nously clock data between a master (e.g. a microcontroller) and a slave (eeprom). fm24c128 is designed to minimize pin count and simplify pc board layout requirements. fm24c128 offers hardware write protection where by the entire memory array can be write protected by connecting wp pin to v cc . the entire memory then becomes unalterable until the wp pin is switched to v ss . ?z?and ??versions of fm24c128 offer very low standby current making them suitable for low power applications. this device is offered in so, tssop and dip packages. fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consump- tion. block diagram features extended operating voltage: 2.5v to 5.5v up to 400 khz clock frequency at 2.5v to 5.5v low power consumption 0.5ma active current typical ?0 a standby current typical ? a standby current typical (l version) 0.1 a standby current typical (lz version) schmitt trigger inputs 64 byte page write mode self timed write cycle (6ms max) hardware write protection for the entire array endurance: up to 100k data changes data retention: greater than 40 years packages: 8-pin dip, 8-pin so and 8-pin tssop temperature range commercial: 0 c to +70 c industrial (e): -40 c to +85 c automotive (v): -40 c to +125 c h.v. generation timing &control e 2 prom array ydec data register xdec control logic word address counter slave address register & comparator start stop logic write lockout ck d in r/w sda scl wp v cc v ss d out a2 a1 a0
2 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom a0 a1 a2 v ss v cc wp scl sda 8 7 6 5 1 2 3 4 fm24c128 connection diagram dual-in-line package (n), so package (mw8) and tssop package (mt8) see package number n08e, m08d and mtc08 pin names v ss ground sda serial data i/o scl serial clock input wp write protect v cc power supply a0, a1, a2 device address inputs
3 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom ordering information fm 24 c xx f lz e yy x letter description blank tube x tape and reel package n 8-pin dip mw8 8-pin soic mt8 8-pin tssop temp. range blank 0 to 70 c e -40 to +85 c v -40 to +125 c voltage operating range blank 4.5v to 5.5v l 2.5v to 5.5v lz 2.5v to 5.5v and <1 a standby current scl clock frequency blank 100khz f 400khz density 128 128k with write protect c cmos interface 24 iic - 2 wire fm fairchild non-volatile memory
4 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom product specifications absolute maximum ratings ambient storage temperature ?5 c to +150 c all input or output voltages with respect to ground 6.5v to ?.3v lead temperature (soldering, 10 seconds) +300 c esd rating 2000v min. operating conditions ambient operating temperature fm24c128 0 c to +70 c fm24c128e -40 c to +85 c fm24c128v -40 c to +125 c positive power supply fm24c128 4.5v to 5.5v fm24c128l 2.5v to 5.5v fm24c128lz 2.5v to 5.5v standard v cc (4.5v to 5.5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.5 1.0 ma f scl = 100 khz i sb standby current v in = gnd or v cc 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage ?.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v low v cc (2.5v to 5 .5v) dc electrical characteristics symbol parameter test conditions limits units min typ max (note 1) i cca active power supply current f scl = 400 khz 0.5 1.0 ma f scl = 100 khz i sb standby current v in = gnd v cc = 2.5v - 4.5v (l) 1 10 a (note 3) or v cc v cc = 2.5v - 4.5v (lz) 0.1 1 a v cc = 4.5v - 5.5v 10 50 a i li input leakage current v in = gnd to v cc 0.1 1 a i lo output leakage current v out = gnd to v cc 0.1 1 a v il input low voltage ?.3 v cc x 0.3 v v ih input high voltage v cc x 0.7 v cc + 0.5 v v ol output low voltage i ol = 2.1 ma 0.4 v capacitance t a = +25 c, f = 100/400 khz, v cc = 5v (note 2) symbol test conditions max units c i/o input/output capacitance (sda) v i/o = 0v 8 pf c in input capacitance (a0, a1, a2, scl) v in = 0v 6 pf note 1: typical values are t a = 25 c and nominal supply voltage (5v). note 2: this parameter is periodically sampled and not 100% tested. note 3: the "l" and "lz" versions can be operated in the 2.5v to 5.5v v cc range. however the i sb values for l and lz are applicable only when v cc is in the 2.5v to 4.5v range.
5 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom ac test conditions input pulse levels v cc x 0.1 to v cc x 0.9 input rise and fall times 10 ns input & output timing levels v cc x 0.3 to v cc x 0.7 output load 1 ttl gate and c l = 100 pf bus timing scl sda in sda out t f t low t high t r t low t aa t dh t buf t su:sta t hd:dat t hd:sta t su:dat t su:sto 0.9v cc 0.1v cc 0.7v cc 0.3v cc read and write cycle limits (standard and low v cc range 2.5v - 5.5v) symbol parameter 100 khz 400 khz units min max min max f scl scl clock frequency 100 400 khz t i noise suppression time constant at scl, sda inputs (minimum v in 100 50 ns pulse width) t aa scl low to sda data out valid 0.3 3.5 0.1 0.9 s t buf time the bus must be free before 4.7 1.3 s a new transmission can start t hd:sta start condition hold time 4.0 0.6 s t low clock low period 4.7 1.5 s t high clock high period 4.0 0.6 s t su:sta start condition setup time 4.7 0.6 s (for a repeated start condition) t hd:dat data in hold time 0 0 ns t su:dat data in setup time 250 120 ns t r sda and scl rise time 1 0.3 s t f sda and scl fall time 300 300 ns t su:sto stop condition setup time 4.7 0.6 s t dh data out hold time 100 50 n s t wr write cycle time 6 6 m s note 4 : the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle. during the write cycle, the fm24c128 bus interface circuits are disabled, sda is allowed to remain high per the bus-level pull-up resistor, and the dev ice does not respond to its slave address. refer "write cycle timing" diagram. ac testing input/output waveforms
6 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom sda scl master transmitter/ receiver slave transmitter/ receiver master transmitter slave receiver master transmitter/ receiver v cc v cc typical system configuration note: due to open drain configuration of sda and scl, a bus-level pull-up resistor is called for, (typical value = 4.7k ? ) sda scl stop condition start condition word n 8th bit ack t wr write cycle timing note: the write cycle time (t wr ) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
7 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom background information (iic bus) extended iic specification is an extension of standard iic speci- fication to allow addressing of eeproms with more than 16kbits of memory on an iic bus. the difference between the two specifications is that extended iic specification defines two bytes of ?rray address?information while standard iic specification defines only one. all other aspects are identical between the two specifications. using two bytes of array address and 3 address signals (a2, a1 and a0), it is now possible to address up to 4 mbits (2 8 * 2 8 * 2 3 * 8 = 4 mbits) of memory on an iic bus. note that due to format difference, it is not possible to have peripherals which follow standard iic specification (e.g. 16k bit eeprom) and peripherals which follow extended iic specifica- tion (e.g. 128k bit eeprom) on a common iic bus. iic bus allows synchronous bi-directional communication be- tween a transmitter and a receiver using a clock signal (scl) and a data signal (sda). additionally there are up to three address signals (a2, a1 and a0) which collectively serve as ?hip select signal?to a device (e.g. eeprom) on the bus. all communication on the iic bus must be started with a valid start condition (by a master), followed by transmittal (by the master) of byte(s) of information (address/data). for every byte of information received, the addressed receiver provides a valid acknowledge pulse to further continue the communica- tion unless the receiver intends to discontinue the communica- tion. depending on the direction of transfer (write or read), the receiver can be a slave or the master. a typical iic communication concludes with a stop condition (by the mas- ter). addressing an eeprom memory location involves sending a command string with the following information: [device type]?device/page block selection]?r/w bit]?array address#1]?array address#0] slave address slave address is an 8-bit information consisting of a device type field (4bits), device/page block selection field (3bits) and read/ write bit (1bit). slave address format device type iic bus is designed to support a variety of devices such as rams, eproms etc., along with eeproms. hence to properly identify various devices on the iic bus, a 4-bit ?evice type?identifier string is used. for eeproms, this 4-bit string is 1-0-1-0. every iic device on the bus internally compares this 4-bit string to its own ?evice type?string to ensure proper device selection. device/page block selection when multiple devices of the same type (e.g. multiple eeproms) are present on the iic bus, then the a2, a1 and a0 address information bits are used in device selection. every iic device on the bus internally compares this 3-bit string to its own physical configuration (a2, a1 and a0 pins) to ensure proper device selection. this comparison is in addition to the ?evice type comparison. in addition to selecting an eeprom, these 3 bits are also used to select a ?age block?within the selected eeprom. each page block is 512kbit (64 k bytes) in size. if an eeprom contains more than one page bock then the selection of a page block within the eeprom is by using a2, a1 and a0 bits. read/write bit last bit of the slave address indicates if the intended access is read or write. if the bit is "1," then the access is read, whereas if the bit is "0," then the access is write. acknowledge acknowledge is an active low pulse on the sda line driven by an addressed receiver to the addressing transmitter to indicate receipt of 8-bits of data. the receiver provides an ack pulse for every 8-bits of data received. this handshake mechanism is done as follows: after transmitting 8-bits of data, the transmitter re- leases the sda line and waits for the ack pulse. the addressed receiver, if present, drives the ack pulse on the sda line during the 9th clock and releases the sda line back (to the transmitter). refer figure 3 . array address#1 this is an 8-bit information containing the most significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device. array address#0 this is an 8-bit information containing the least significant 8-bits of 16-bit memory array address of a location to be selected within a page block of the device. device type identifier device/page block selection 1 0 1 0 a2 a1 a0 r/w (lsb)
8 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom pin descriptions serial clock (scl) the scl input is used to clock all data into and out of the device. serial data (sda) sda is a bi-directional pin used to transfer data into and out of the device. it is an open drain output and may be wire ored with any number of open drain or open collector outputs. write protect (wp) if tied to v cc , program operations onto the entire memory will not be executed. read operations are possible. if tied to v ss , normal operation is enabled, read/write over the entire memory is possible. this feature allows the user to assign the entire memory as rom which can be protected against accidental programming. when write is disabled, slave address and word address will be acknowl- edged but data will not be acknowledged. this pin has an internal pull-down circuit. however, on systems where write protection is not required it is recommended that this pin is tied to v ss . device selection inputs a2, a1 and a0 (as appropriate) these inputs collectively serve as chip select signal to an eeprom when multiple eeproms are present on the same iic bus. hence these inputs should be connected to v cc or v ss in a unique manner to allow proper selection of an eeprom amongst multiple eeproms. during a typical addressing sequence, every eeprom on the iic bus compares the configuration of these inputs to the respective 3 bit device/page block selection information (part of slave address) to determine a valid selection. for e.g. if the 3 bit device/page block selection is 1-0-1, then the eeprom whose device selection inputs (a2, a1 and a0) are connected to v cc -v ss -v cc respectively, is selected. device operation the fm24c128 supports a bi-directional bus oriented protocol. the protocol defines any device that sends data onto the bus as a transmitter and the receiving device as the receiver. the device controlling the transfer is the master and the device that is controlled is the slave. the master will always initiate data transfers and provide the clock for both transmit and receive operations. therefore, the fm24c128 will be considered a slave in all applications. clock and data conventions data states on the sda line can change only during scl low. sda state changes during scl high are reserved for indicating start and stop conditions. refer figure 1 . start condition all commands are preceded by the start condition, which is a high to low transition of sda when scl is high. the fm24c128 continuously monitors the sda and scl lines for the start condi- tion and will not respond to any command until this condition has been met. refer figure 2 . stop condition all communications are terminated by a stop condition, which is a low to high transition of sda when scl is high. the stop condition is also used by the fm24c128 to place the device in the standby power mode. refer figure 2 . fm24c128 array addressing during read/write operations, addressing the eeprom memory array involves in providing 2 address bytes, word address 1 and word address 0." however on fm24c128 only the 6 least significant bits (lsb) of word address 1 byte are used in decoding the access location. the remaining 2 bits are not used and are recommended to be set to 0." all 8 bits of the word address 0 byte are used in decoding the access location.
9 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom data validity (figure 1) start and stop definition (figure 2) scl from master data output from transmitter data output from receiver 189 start condition acknowledge pulse t aa t dh sda scl start condition stop condition scl data stable data change sda acknowledge response from receiver (figure 3)
10 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom write operations byte write for byte write operation, two bytes of address are required after the slave address. these two bytes select 1 out of the 16,384 locations in the memory. the master provides these two address bytes and for each address byte received, fm24c128 responds with an acknowledge pulse. master then provides a byte of data to be written into the memory. upon receipt of this data, fm24c128 responds with an acknowledge pulse. the master then terminates the transfer by generating a stop condition, at which time the fm24c128 begins the internal write cycle to the memory. while the internal write cycle is in progress the fm24c128 inputs are disabled, and the device will not respond to any requests from the master for the duration of t wr . refer figure 4 for the address, acknowledge and data transfer sequence. page write to minimize write cycle time, fm24c128 offers page write feature, which allows simultaneous programming of up to 64 contiguous bytes. to facilitate this feature, the memory array is organized in terms of pages . a page consists of 64 contiguous byte locations starting at every 64-byte address boundary (for example, starting at array address 0x0000, 0x0040, 0x0080 etc.). page write operation is confined to a single page. in other words a page write operation will not cross over to locations on the next page but will roll over to the beginning of the same page whenever end of page is reached and additional data bytes are a continued to be provided. a page write operation can be initiated to begin at any location within a page (starting address of the page write operation need not be the starting address of a page). s t o p a c k a c k bus activity: master sda line 1010 bus activity a c k data n data n+63 a c k word address (1) word address (0) slave address s t a r t s t o p a c k bus activity: master sda line bus activity: eeprom a c k data a c k a c k word address (1) word address (0) slave address s t a r t page write is initiated in the same manner as the byte write operation; but instead of terminating the cycle after transmitting the first data byte, the master can further transmit up to 63 more bytes. after the receipt of each byte, fm24c128 will respond with an acknowledge pulse, increment the internal address counter to the next address, and is ready to accept the next data. if the master should transmit more than 64 bytes prior to generating the stop condition, the address counter will roll over and previously loaded data will be re-loaded. as with the byte write operation, all inputs are disabled until completion of the internal write cycle. refer figure 5 for the address, acknowledge, and data transfer sequence. acknowledge polling once the stop condition is issued to indicate the end of the host s write operation, the fm24c128 initiates the internal write cycle. ack polling can be initiated immediately. this involves issuing the start condition followed by the slave address for a write operation. if the fm24c128 is still busy with the write operation, no ack will be returned. if the fm24c128 has completed the write operation, an ack will be returned and the host can then proceed with the next read or write operation. write protection programming of the entire memory will not take place if the wp pin of the fm24c128 is connected to v cc . the fm24c128 will respond to slave and byte addresses; but if the memory accessed is write protected by the wp pin, the fm24c128 will not generate an acknowledge after the first byte of data has been received. thus the program cycle will not be started when the stop condition is asserted. byte write (figure 4) page write (figure 5)
11 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom s t o p a c k no a c k bus activity: master sda line 01 bus activity: eeprom a c k a c k word address (1) word address (0) slave address slave address data a c k s t a r t s t a r t s t o p a c k bus activity: master sda line bus activity: eeprom a c k data n + x a c k data n + 2 data n +1 data n +1 a c k no a c k slave address read operations read operations are initiated in the same manner as write operations, with the exception that the r/w bit of the slave address is set to a one. there are three basic read operations: current address read, random read, and sequential read. current address read internally the fm24c128 contains an address counter that main- tains the address of the last byte accessed, incremented by one. therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n + 1. upon receipt of the slave address with r/w set to "1," the fm24c128 issues an acknowledge and transmits the eight bit word. the master will not acknowledge the transfer but does generate a stop condition, and therefore the fm24c128 discon- tinues transmission. refer figure 6 for the sequence of address, acknowledge and data transfer. random read random read operations allow the master to access any memory location in a random manner. prior to issuing the slave address with the r/w bit set to "1," the master must first perform a dummy write operation. the master issues the start condition, slave address with the r/w bit set to "0" and then the byte address. after the byte address acknowledge, the master imme- diately issues another start condition and the slave address with the r/w bit set to one. this will be followed by an acknowledge from the fm24c128 and then by the eight bit word. the master will not acknowledge the transfer but does generate the stop condition, and therefore the fm24c128 discontinues transmis- sion. refer figure 7 for the address, acknowledge, and data transfer sequence. sequential read sequential reads can be initiated as either a current address read or random access read. the first word is transmitted in the same manner as the other read modes; however, the master now responds with an acknowledge, indicating it requires additional data. the fm24c128 continues to output data for each acknowl- edge received. the read operation is terminated by the master not responding with an acknowledge or by generating a stop condi- tion. the data output is sequential with the data from address n followed by the data from n + 1. the address counter for read operations increments all word address bits, allowing the entire memory contents to be serially read during one operation. after the entire memory has been read, the counter "rolls over" to the beginning of the memory. fm24c128 continues to output data for each acknowledge received. refer figure 8 for the address, acknowledge, and data transfer sequence. s t o p data a c k no a c k s t a r t slave address bus activity: master sda line bus activity: eeprom 1 0 1 0 1 current address read (figure 6) random read (figure 7) sequential read (figure 8)
12 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom 8-pin molded small outline package (mw8) package number m08d physical dimensions inches (millimeters) unless otherwise noted 0.206 0.004 1. 0.050 bsc 0.80 max. 0.325 max. 0.305 min. 1. 2. 3. 4. does not include mold flash, protrusions or gate burrs. mold flash, protrusions and gate burrs shall not exceed 0.006 inch per side does not include inter-lead flash or protrusions. inter-lead flash and protrusions shall not exceed 0.010 inch per side. this part is compliant with eiaj specification ed-7402-1. lead span/stand off height/coplanarity are considered as special characteristic.(s) 2. 2. 0.0098 max. 0.0020 min. 0.030 max. 0.020 min. 0.208 0.004 7 ref all side. 0.032 0.002 0.008 +0.0015 -0.0005 leadframe thickness 0 - 8 0.019 max. 0.014 min. 0.206 0.004 note : 8-lead molded thin shrink small outline package (mt8) package number mtc08 0.114 - 0.122 (2.90 - 3.10) 0.123 - 0.128 (3.13 - 3.30) 0.246 - 0.256 (6.25 - 6.5) 14 85 0.169 - 0.177 (4.30 - 4.50) (7.72) typ (4.16) typ (1.78) typ (0.42) typ (0.65) typ 0.002 - 0.006 (0.05 - 0.15) 0.0256 (0.65) typ. 0.0433 (1.1) max 0.0075 - 0.0118 (0.19 - 0.30) pin #1 ident 0.0035 - 0.0079 0 -8 0.020 - 0.028 (0.50 - 0.70) 0.0075 - 0.0098 (0.19 - 0.25) seating plane gage plane see detail a notes: unless otherwise specified 1. reference jedec registration mo153. variation aa. dated 7/93 land pattern recommendation detail a typ. scale: 40x
13 www.fairchildsemi.com fm24c128 rev. d fm24c128 ?128k-bit standard 2-wire bus interface serial eeprom physical dimensions inches (millimeters) unless otherwise noted fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fai rchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild's products are not authorized for use as critical components in life support devices or systems without the express w ritten approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to perform, when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably ex- pected to cause the failure of the life support device or system, or to affect its safety or effectiveness. fairchild semiconductor fairchild semiconductor fairchild semiconductor fairchild semiconductor americas europe hong kong japan ltd. customer response center fax: +44 (0) 1793-856858 8/f, room 808, empire centre 4f, natsume bldg. tel. 1-888-522-5372 deutsch tel: +49 (0) 8141-6102-0 68 mody road, tsimshatsui east 2-18-6, yushima, bunkyo-ku english tel: +44 (0) 1793-856856 kowloon. hong kong tokyo, 113-0034 japan fran ? ais tel: +33 (0) 1-6930-3696 tel; +852-2722-8338 tel: 81-3-3818-8840 italiano tel: +39 (0) 2-249111-1 fax: +852-2722-8383 fax: 81-3-3818-8841 molded dual-in-line package (n) package number n08e 0.373 - 0.400 (9.474 - 10.16) 0.092 (2.337) dia + 1234 8765 0.250 - 0.005 (6.35 0.127) 87 0.032 0.005 (0.813 0.127) pin #1 option 2 rad 1 0.145 - 0.200 (3.683 - 5.080) 0.130 0.005 (3.302 0.127) 0.125 - 0.140 (3.175 - 3.556) 0.020 (0.508) min 0.018 0.003 (0.457 0.076) 90 4 typ 0.100 0.010 (2.540 0.254) 0.040 (1.016) 0.039 (0.991) typ. 20 1 0.065 (1.651) 0.050 (1.270) 0.060 (1.524) pin #1 ident option 1 0.280 min 0.300 - 0.320 (7.62 - 8.128) 0.030 (0.762) max 0.125 (3.175) dia nom 0.009 - 0.015 (0.229 - 0.381) 0.045 0.015 (1.143 0.381) 0.325 +0.040 -0.015 8.255 +1.016 -0.381 95 5 0.090 (2.286) (7.112) ident
product folder - fairchild p/n fm24c128l - 128k-bit 2-wire bus interface serial eeprom w/ full array write protect fairchild semiconductor space space space search | parametric | cross reference space product folders and datasheets application notes space space space find products home >> find products >> space space space space products groups space analog and mixed signal discrete interface logic microcontrollers non-volatile memory optoelectronics markets and applications new products product selection and parametric search cross-reference search technical information buy products technical support my fairchild company fm24c128l 128k-bit 2-wire bus interface serial eeprom w/ full array write protect related links request samples dotted line how to order products dotted line product change notices (pcns) dotted line support dotted line distributor and field sales representatives dotted line quality and reliability dotted line design tools contents general description | features | product status/pricing/packaging general description fm24c128 is a 128kbit cmos non-volatile serial eeprom organized as 16k x 8 bit memory. this device confirms to extended iic 2-wire protocol that allows accessing of memory in excess of 16kbit on an iic bus. this serial communication protocol uses a clock signal (scl) and a data signal (sda) to synchronously clock data between a master (e.g. a microcontroller) and a slave (eeprom). fm24c128 is designed to minimize pin count and simplify pc board layout requirements. fm24c128 offers hardware write protection where by the entire memory array can be write protected by connecting wp pin to v cc . the entire memory then becomes unalterable until the wp pin is switched to v ss . "lz" and "l" versions of fm24c128 offer very low standby current making them suitable for low power applications. this device is offered in so, tssop and dip packages. fairchild eeproms are designed and tested for applications requiring high endurance, high reliability and low power consumption. back to top features space datasheet download this datasheet pdf e-mail this datasheet [e- mail] this page print version file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c128l.html (1 of 3) [26-jul-2002 3:53:14 pm]
product folder - fairchild p/n fm24c128l - 128k-bit 2-wire bus interface serial eeprom w/ full array write protect l extended operating voltage: 2.5v to 5.5v l up to 400 khz clock frequency at 2.5v to 5.5v l low power consumption m 0.5ma active current typical m 10a standby current typical m 1a standby current typical (l version) m 0.1a standby current typical (lz version) l schmitt trigger inputs l 64 byte page write mode l self timed write cycle (6ms max) l hardware write protection for the entire array l endurance: up to 100k data changes l data retention: greater than 40 years l packages: 8-pin dip, 8-pin so and 8- pin tssop l temperature range m commercial: 0c to +70c m industrial (e): -40c to +85c m automotive (v): -40c to +125c back to top product status/pricing/packaging product product status pricing* package type leads package marking packing method fm24c128lem8x full production $1.29 soic 8 $y&z&2&t 24c128 le tape reel fm24c128lm8x full production $1.29 soic 8 $y&z&2&t 24c128 l tape reel fm24c128lem8 full production $1.29 soic 8 $y&z&2&t 24c128 le rail fm24c128lvmt8 full production $1.29 tssop 8 &2&t $y128 &z24128 lv rail fm24c128lm8 full production $1.29 soic 8 $y&z&2&t 24c128 l rail * 1,000 piece budgetary pricing back to top file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c128l.html (2 of 3) [26-jul-2002 3:53:14 pm]
product folder - fairchild p/n fm24c128l - 128k-bit 2-wire bus interface serial eeprom w/ full array write protect space space home | find products | technical information | buy products | support | company | contact us | site index | privacy policy ? copyright 2002 fairchild semiconductor space space file:///h|/imaging/bitting/cpl/20020725_1/07252002_10/fair/07252002/fm24c128l.html (3 of 3) [26-jul-2002 3:53:14 pm]

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